Co-Packaged Optics (CPO) for Advanced Cryocooled Electro-Optical/Infrared (EO/IR) Sensors

STTR · Phase: BOTH · Topic DON27TZ02-NV001 · Solicitation 27.TZ

Current Department of the Navy (DON) platforms are generating unprecedented volumes of data via advanced radar, SIGINT, and high-resolution imaging sensors. Processing of this data at the tactical edge requires extreme bandwidth but can consume excessive powers, creating significant thermal and signal integrity bottlenecks [Ref 1]. Specifically, for advanced EO/IR sensors that operate in cryocooled temperatures (e.g., 70-140K), the excessive power required to electrically read out the data, i.e., transmit from cold space and receive in warm space, presents a challenging limitation on the size, weight, and power (SWaP) of an integrated dewar cooler assembly. Fiber optics and photonic integrated circuits (PICs) are key optical readout technologies that can offer extreme bandwidth, low power consumption, and mature fabrication but require integrated packaging solutions for next generation DON systems [Ref 2]. CPO offers an integrated solution that considers both optical and electrical elements in EO/IR sensor design, optimizing performance, reliability, and manufacturability. CPO brings the optical transceiver components directly into the same package as the readout integrated circuit (ROIC). This minimizes the electrical channel length or completely eliminates it with photonic interconnects, fundamentally lowering power consumption (energy per bit) and enabling massive bandwidth scaling [Refs 1-4]. To date, commercial CPO solutions are primarily designed for room temperature, climate-controlled hyperscale AI data centers. This STTR topic seeks to adapt and innovate current CPO technologies for the stringent Size, Weight, Power, and Cost (SWaP-C) and packaging (cryogenically cooled) constraints of advanced Navy EO/IR sensing platforms. The focus of the topic is on the design and development of a CPO architecture that integrates with the ROIC layer of a typical EO/IR sensor chip assembly, enables high-bandwidth cold to warm readout, and operates in cryocooled temperatures. Proposals must address critical challenges, including: 1. ROIC compatibility: PIC interconnect architecture that is compatible with conventional analog and mixed-signal digital ROICs designed in <180 nm node foundries, optimal number of fiber outputs to meet total ROIC bandwidth. 2. Thermal Management: Dissipating heat effectively when dense photonics and ROICs are co-located in a cryocooled integrated dewar assembly. Minimize PIC power consumption to less than 20 mW. 3. Power Efficiency: Choice of electrical-optical conversion scheme and minimizing power consumption (e.g., half-wave voltage for EO modulators, Vpi), PIC waveguide propagation loss, PIC to fiber input/output coupling losses, and stray light scatter. 4. Integration & Packaging: Complementary metal–oxide–semiconductor (CMOS)-compatible substrate materials, 2.5D/3D integration techniques, and cost-effective scalable manufacturing processes.

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2026.11.06

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