Additive Manufacturing for Flexible Electronics

SBIR · Phase: BOTH · Topic DME26BZ05-NV001 · Solicitation 26.BZ

Additive manufacturing, also referred to as 3D printing, has seen innovation in several critical areas in the field of electronics packaging and assembly from wafer level to printed circuit boards for low volume manufacturing and prototyping. Ceramic interposers are being manufactured using vat photopolymerization technologies to create substrates with channels for interconnects, that are backfilled through the process of metal infiltrations [1] The unique geometries enabled by the layer-to-layer technologies allow for routing options not possible with traditional fabrication techniques or fabrication quantities that are not economically viable. Semiconductor die pads to package substrate interconnects through 3D printed traces have been explored to replace traditional wire bonding connections. This enables smaller form factors as the wire height requirements are replaced with flat aerosol jet printed conductive traces created using nanoparticle inks [3]. The formulations of the conductive ink still pose challenges with material compatibility between interfaces [4], electrical resistance, and limited thermal operational ranges as each company creates material best suited to their printing system [2]. Printed interconnects open the doors for faster turnaround time, performance improvement through impedance matching for packaged devices [3], shorter interconnect lengths, and chip scaling through tool path alterations [4]. Additively manufactured printed circuit board assemblies which utilized printed traces and interconnects have also integrated printed passives such as resistors and capacitors into the boards [5]. These targets eliminating the need to pick and place passives in the assembly process as potentially any passive desired could be printed onto the boards. The three-dimensions fabrication methods also allow for the resistance values to be adjusted within a limited space. Virtually every DoW system with electronics requires PCB manufacturing. Commercially available Substrate Manufacturing techniques and Advanced Packaging techniques are extremely expensive and require long lead times and are therefore not conducive to High Mix - Low Volume manufacturing efforts. It is desired to improve and validate existing additive manufacturing methods for use on government and commercial systems. Existing additive substrate fabrication and additive advanced packaging methods have been proven to be flexible, adaptable, and cost effective, there remains an undefined reliability risk. DoW is looking to enable these technologies. Specifically, by obtaining reliability data using MIL-STD quality and reliability metrics, these additive manufacturing technologies could become a viable alternative to traditional substrate manufacturing and advanced packaging. As a Phase I study, DoW is seeking the feasibility of developing a prototype via this effort directly comparable to existing Radio Frequency multichip modules (MCMs) currently used by the DoW. Additionally, the feasibility study may offer additional miniaturization or other forms of improvements that are of extreme interest to DoW. If such technology can produce prototypes with reliability comparable to standard manufacturing or reliable enough to fulfill target DoW missions, the additive manufacturing technologies could be used extensively on relevant microelectronic designs to reduce cost and manufacturing timelines for DoW Programs.

SBIR/STTR 은 미국 중소기업만 지원할 수 있습니다(Small Business Act 법정 요건). • 계열사를 포함해 상시 종업원 500명 이하 • 미국 시민 또는 영주권자 1인 이상이 50%를 초과해 직접 소유·지배 • 미국 내 사업장을 두고 주로 미국 내에서 사업을 영위할 것 • 수행책임자(PI)의 주된 근무처가 신청 기업일 것 출처: https://www.sbir.gov/faq/eligibility-requirements

Primary country

🇺🇸 United States

Also eligible

None

Foreign companies

No

Local entity

Required

Location condition

미국 내 사업장을 두고 미국 시민·영주권자가 50%를 초과해 소유한 중소기업만 신청할 수 있습니다(법정 요건).

Document requirements were not captured (needs verification). Check the official announcement.

Application process not captured.

Evaluation process not captured.

Process steps were not captured.

Generated by local:rules-v1 · 3h ago

The announcement does not say what has to be submitted, so the disclosure exposure cannot be judged. the scope of the material requested is not stated. The awarding body is U.S. Department of War — DMEA. 8 fields could not be read and must be checked in the announcement and the grant agreement.

This assessment is derived from the stored announcement, document and contract fields. Anything the source does not state is marked "needs verification" — it never asserts that your idea will be taken. Generated by local:rules-v1 · 3h ago

Official URL

https://www.dodsbirsttr.mil/topics-app/

Application URL

https://www.dodsbirsttr.mil/topics-app/

Last fetched

2026.08.20

Human review

Not reviewed — check the official announcement

First seen

2026.08.20

Data status

Auto-collected, not reviewed

AI enrichment

local:rules-v1 · 3h ago